1. Field of Invention
The present invention relates to integrated circuit memories, and more particularly to multiple binary digit (bit) per cell metal oxide semiconductor (MOS) integrated circuit memory devices.
2. Description of Related Art
The cost of integrated circuit memory devices is closely related to the amount of area on an integrated circuit that is required to store a given amount of data, a parameter often referred to as the density of the device. By saving area on an integrated circuit, a manufacturer is able to make more chips with a given wafer in the fabrication factory. More chips per wafer translates directly to cost savings which can be passed on to the consumers of the memory devices.
One approach for increasing the density of memory devices is to store more than one bit per memory cell. Thus for example, the ability to store two bits per cell provides twice the data density on an integrated circuit.
Multiple bit per cell technologies have been developed for floating gate memory devices. See U.S. Pat. No. 5,163,021 to Mehrotra, et al. However, the floating gate memory approach involves complex charging and discharging of the floating gates, and difficult sensing technology, which increases the complexity and reduces the reliability of the devices.
Accordingly, there is a need for a simpler, reliable, low cost technique for implementing multiple bits per memory cell in an integrated circuit.
The present invention provides a technique for storing multiple bits per cell in an integrated circuit having asymmetric memory cells. A substantial source of error is found in memory arrays comprising symmetric memory cells. The source of error is alternative current paths through neighboring memory cells. These alternate current paths can alter the drain read current of the cell of interest so that it is read as a different type of cell. The asymmetric cells are adapted to dramatically reduce source read current. Appropriate placement of the asymmetric cells in a memory array makes use of the reduced source read current to ensure that multilevel cells in the memory device are accurately read. The invention thereby eliminates the error from alternative current paths.
In some embodiments of the invention, the memory cell has a drain, a source, and a channel disposed between the drain and the source, all of which are provided in a substrate of the memory cell. In the asymmetric memory cell, the channel is spaced laterally from the drain. The lateral distance separating the gate from the drain is an offset. An offset region is disposed in the substrate. The offset region is disposed between the drain and the channel.
The memory cell has a plurality of bits stored in the channel. The MOS device has sets of memory cells. Memory cells of a particular set have a different threshold voltage than the memory cells from a different set. The threshold voltages depend upon a dopant concentration in the channel regions. Each bit of information corresponds to the threshold voltage of the cell.
A first group of embodiments of the invention provides a method for forming multilevel cells in a memory array on a substrate. The memory array has a plurality of multilevel cells. Each multilevel cell comprises a gate, a gate oxide, a channel, a drain, and a source. The gate is disposed above the gate oxide. The gate oxide has a top. The channel is disposed in the substrate and is aligned with the gate. The drain is disposed in the substrate. The drain is located on a first side of the gate. The source is disposed in the substrate and disposed on a second side of the gate. The second side is opposite the first side.
The method for forming the multilevel cell comprises directing a source only implant, forming a first spacer, and directing a source/drain implant. The source only implant is directed into the source of each multilevel cell.
The first spacer is formed on the first side of the gate and extends upwards from the top of the gate oxide. The first spacer has a first spacer width. The first spacer width is adapted to provide an offset between the channel and the drain of each multilevel cell.
The source/drain implant is directed into both the source and the drain of each multilevel cell. Through these steps an offset region is formed. The offset region is disposed between the channel and the drain. The offset region is adapted to inhibit a source read current.
For some embodiments of the first group, the first spacer width is in a range from approximately 0.05 micrometers to approximately 0.20 micrometers. The offset is smaller than the first spacer width. For some embodiments the size of the offset is greater than approximately fifty percent ( greater than 50%) of the first spacer width.
For some embodiments of the first group, the method further comprises directing a first channel implant, directing a first code implant, directing a second code implant, forming the gate oxide, depositing a first conductive layer, patterning the gate from first conductive layer, and masking the drain; prior to directing the source only implant.
The first channel implant is directed into all of the multilevel cell channels. The first code implant is directed into a first selected group of multilevel cell channels. The second code implant is directed into a second selected group of multilevel cell channels. The second code implant has a different projected range than the first channel implant. The second code implant also has a different projected range, i.e., depth profile, than the first code implant. Each multilevel cell has a bit code selected from a group of four different bit codes. Each of the four different bit codes corresponds to a specific combination of the first channel implant, the first code implant, and the second code implant.
More generally, the code implants may be directed as n code implants into n different selected groups of multilevel memory cell channels. Each of the n implants has a set of implant characteristics different than the other nxe2x88x921 code implants. Each multilevel memory cell can have a bit code selected from a group of 2n different bit codes. Each of the 2n different bit codes corresponds to a specific combination of the first channel implant and the n code implants. For some embodiments, the set of implant characteristics comprises projected range and the number of implanted ions.
For some embodiments of the first group, the method further comprises depositing a second conductive layer and patterning the second conductive layer; after directing the source/drain implant.
For some embodiments of the first group, the method further comprises forming a second spacer on the second side of the gate, the second spacer extending upwards from the top of the gate oxide.
A second group of embodiments of the invention provides a MOS memory cell in an integrated circuit. The integrated circuit has a substrate. The MOS memory cell has a source formed in the substrate and a gate. The MOS memory cell also has a gate oxide disposed between the substrate and the gate. The MOS memory cell further comprises a drain, a channel, and an offset region. The drain is formed in the substrate and has a width.
The channel is formed in the substrate. The channel is in contact with the gate oxide. The channel is aligned with the gate. The channel extends at least a portion of the distance from the source towards the drain. The channel is separated from the drain by an offset. The channel is adapted to store multiple bits.
For some embodiments, the channel is adapted to form a depletion layer in a region of the channel proximal to the gate oxide in response to a gate voltage.
The offset region has an initial conduction state. The offset region is adapted to maintain the original conduction state proximal to the gate oxide in response to the gate voltage. The MOS memory cell has a drain read current corresponding to a drain voltage and a source read current corresponding to a source voltage. The source voltage is equal to the drain voltage. The drain read current has a different value than the source read current.
For some of the embodiments of the second group, the source read current is smaller than the drain read current, the offset region is adapted to form a depletion layer proximal to the gate oxide in response to the drain voltage, the offset is in a range from approximately 0.02 micrometers to approximately 0.20 micrometers, and the offset region is adapted to maintain its original conduction state proximal to the gate oxide in response to the source voltage.
For some embodiments of the second group, the gate has a gate width. The gate also has a first side, a second side opposite the first side, a bottom, and a top. The gate width is the distance between the first side and the second side. The gate is disposed between the source and the drain. The gate is disposed above the gate oxide. The drain is disposed on the first side and the source is disposed on the second side. The gate width is smaller than the distance between the source and the drain. The gate oxide has a top. In this embodiment, the MOS memory cell further comprises a first spacer disposed along the first side of the gate. The first spacer extends upwards from the top of the gate oxide. The first spacer also has a first spacer width.
A third group of embodiments of the invention provides an integrated circuit comprising an array of memory cells, a bit line, and a word line. The memory cells comprise transistors having channels in channel regions of a substrate. Selected memory cells in the array store multiple bits in their channels.
The word line and the bit line are coupled respectively with rows and columns of memory cells in the array by which to read data stored in the array. The bit line comprises a first patterned layer of the integrated circuit. The word line comprises a second patterned layer of the integrated circuit.
Each of the selected memory cells has a source formed in the substrate, a gate, and a gate oxide disposed between the substrate and the gate. Each of the selected memory cells further comprises an asymmetric drain, a channel, and an offset region. The asymmetric drain is formed in the substrate and has a width.
The channel is formed in the substrate. The channel is in contact with the gate oxide. The channel is aligned with the gate. The channel extends from the source towards the asymmetric drain. The channel is separated from the asymmetric drain by an offset. The channel is adapted to store multiple bits. The channel is adapted to form a depletion layer in a region of the channel proximal to the gate oxide in response to a gate voltage.
The offset region has an initial conduction state. The offset region is adapted to maintain the original conduction state proximal to the gate oxide in response to the gate voltage.
Each of the selected memory cells has a drain read current corresponding to a drain voltage and a source read current corresponding to a source voltage. In response to the application of the source voltage at a first time and the drain voltage at second time, current in the integrated circuit flows in a first direction at the first time and a second directions at the second time. The second direction is opposite the first direction. The source voltage is equal to the drain voltage. The drain read current has a different value than the source read current.
The offset of each selected memory cell transistor is sufficiently large to ensure that the selected memory cell transistors can only be accurately read by the corresponding word lines and corresponding bit lines in one direction.
For some embodiments of the third group, the offset is in a range from approximately 0.02 micrometers to approximately 0.20 micrometers. The offset region is adapted to form a depletion layer proximal to the gate oxide in response to the drain voltage, and the offset region is adapted to maintain the initial conduction state proximal to the gate oxide in response to the source voltage.
For some of the embodiments of the third group, the gate of each of the selected memory cells is addressable by a corresponding word line. The integrated circuit further comprises a sense amplifier, a ground, a first selected memory cell transistor, and a second selected memory cell transistor.
The sense amplifier has a conductor, a first side, and a second side. The ground has a conductor, a first side, and a second side. The bit line is disposed proximal to the ground conductor. The bit line is disposed on the first side of the ground conductor. The bit line is disposed proximal to the sense amplifier conductor. The bit line is disposed on the second side of the sense amplifier conductor.
The first selected memory cell transistor is disposed between the bit line and the second side of the sense amplifier conductor. The drain of the first selected memory cell transistor is in communication with the sense amplifier conductor.
The second selected memory cell transistor is disposed between the bit line and the first side of the ground conductor. The drain of the second selected memory cell transistor is in communication with the ground conductor. The first selected memory cell transistor and the second selected memory cell transistor have a common source. The bit line is in communication with the common source of the first and second selected memory cell transistors. Wherein, the first memory cell transistor can only be accurately read by the corresponding word line and the corresponding bit line in a first direction. The second memory cell transistor can only be accurately read by the corresponding word line and the corresponding bit line in a second direction. The second direction is opposite the first direction.
For some of the embodiments the integrated circuit further comprises a sense amplifier, a ground, a first selected memory cell transistor, and a second selected memory cell transistor. For these embodiments, the first direction is from the drain of the first selected memory cell to the source of the first selected memory cell. The second direction is from the drain of the second selected memory cell transistor to the source of the second selected memory cell transistor.
A portion of the second direction current flows from the source of the first selected memory cell transistor to the drain of the first selected memory cell transistor. The portion of the second direction current in the first selected memory cell transistor is less than forty percent of the second direction current of the second selected memory cell transistor. A portion of the first direction current flows from the source of the second selected memory cell transistor to the drain of the second selected memory cell transistor. The portion of the first direction current in the second selected memory cell transistor is less than forty percent of the first direction current of the first selected memory cell transistor.
A fourth group of embodiments of the invention provides a method of reading a memory cell having an offset. The method comprises providing the memory cell, where the memory cell is an asymmetric memory cell. For some embodiments in this group, the asymmetric cell is a multilevel cell.